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0.5 cmos, 1.8 v to 5.5 v, dual spdt/2:1 mux, mini lfcsp ADG854 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features 0.8 typical on resistance less than 1 maximum on resistance at 85c 1.8 v to 5.5 v single supply high current carrying capability: 300 ma continuous rail-to-rail switching operation fast-switching times: <17 ns typical power consumption: <0.1 w 1.30 mm 1.60 mm mini lfcsp applications cellular phones pdas mp3 players power routing battery-powered systems pcmcia cards modems audio and video signal routing communication systems functional block diagram s1a s1b in1 in2 d1 ADG854 switches shown for a logic 1 input d2 s2a s2b 07087-001 figure 1. general description the ADG854 is a low voltage cmos device containing two independently selectable single-pole, double-throw (spdt) switches. this device offers ultral ow on resistance of <1 over the full temperature range. the ADG854 is fully specified for 5.5 v and 3.3 v supply operation. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. the ADG854 exhibits break-before-make switching action. the ADG854 is available in a 1.3 mm 1.6 mm 10-lead mini lfcsp. product highlights 1. <1 over full temperature range of C40c to +85c. 2. single 1.8 v to 5.5 v operation. 3. compatible with 1.8 v cmos logic. 4. high current handling capability: 300 ma continuous current per channel. 5. low thd + n: 0.08% typical. 6. 1.30 mm 1.60 mm mini lfcsp.
ADG854 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution...................................................................................5 pin configurations and function description ..............................6 typical performance characteristics ..............................................7 test circuits ..................................................................................... 10 terminology .................................................................................... 12 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 13 revision history 6/08revision 0: initial version
ADG854 rev. 0 | page 3 of 16 specifications v dd = 4.2 v to 5.5v, gnd = 0 v, unless otherwise noted. table 1. parameter +25c ?40c to +85c unit test conditions/comments analog switch analog signal range 0 to v dd v on resistance, r on 0.8 typ v dd = 4.2 v, v s = 0 v to v dd , i ds = 100 ma; see figure 16 0.85 1 max on resistance match between channels, ?r on 0.02 typ v dd = 4.2 v, v s = 0 v to v dd , i ds = 100 ma 0.04 max on resistance flatness, r flat (on) 0.17 typ v dd = 4.2 v, v s = 0 v to v dd , i ds = 100 ma 0.23 max leakage currents v dd = 5.5 v source off leakage, i s (off ) 10 pa typ v s = 0.6 v/4.2 v, v d = 4.2 v/0.6 v; see figure 17 channel on leakage, i d , i s (on) 30 pa typ v s = v d = 0.6 v or 4.2 v; see figure 18 digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.002 a typ v in = v gnd or v dd 0.05 a max digital input capacitance, c in 2.5 pf typ dynamic characteristics 1 t on 17 ns typ r l = 50 , c l = 35 pf 23 28 ns max v s = 3 v/0 v; see figure 19 t off 6 ns typ r l = 50 , c l = 35 pf 8.5 9.2 ns max v s = 3 v; see figure 19 break-before-make time delay, t bbm 14 ns typ r l = 50 , c l = 35 pf 8 ns min v s1 = v s2 = 1.5 v; see figure 20 charge injection 30 pc typ v s = 1.5 v, r s = 0 , c l = 1 nf; see figure 21 off isolation ?75 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 22 channel-to-channel crosstalk ?85 db typ s1a to s2a/s1b to s2b, r l = 50 , c l = 5 pf, f = 100 khz; see figure 25 ?73 db typ s1a to s1b/s2a to s2b, r l = 50 , c l = 5 pf, f = 100 khz; see figure 24 total harmonic distortion + noise, thd + n 0.08 % typ r l = 32 , f = 20 hz to 20 khz, v s = 3.5 v p-p insertion loss ?0.06 db typ r l = 50 , c l = 5 pf; see figure 23 ?3 db bandwidth 100 mhz typ r l = 50 , c l = 5 pf; see figure 23 c s (off ) 19.5 pf typ c d , c s (on) 50 pf typ power requirements v dd = 5.5 v i dd 0.002 a typ digital inputs = 0 v or 5.5 v 1.0 a max 1 guaranteed by design, not subject to production test.
ADG854 rev. 0 | page 4 of 16 v dd = 2.7 v to 3.6 v, gnd = 0 v, unless otherwise noted. table 2. parameter +25c ?40c to +85c unit test conditions/comments analog switch analog signal range 0 to v dd v on resistance, r on 1.3 typ v dd = 2.7 v, v s = 0 v to v dd , i ds = 100 ma; see figure 16 1.5 1.7 max on resistance match between channels, ?r on 0.03 typ v dd = 2.7 v, v s = 0.6 v, i ds = 100 ma 0.05 max on resistance flatness, r flat (on) 0.48 typ v dd = 2.7 v, v s = 0 v to v dd , i ds = 100 ma 0.66 max leakage currents v dd = 3.6 v source off leakage, i s (off ) 10 pa typ v s = 0.6 v/3.3 v, v d = 3.3 v/0.6 v; see figure 17 channel on leakage, i d , i s (on) 30 pa typ v s = v d = 0.6 v or 3.3 v; see figure 18 digital inputs input high voltage, v inh 1.35 v min input low voltage, v inl 0.7 v max input current i inl or i inh 0.002 a typ v in = v gnd or v dd 0.05 a max digital input capacitance, c in 4 pf typ dynamic characteristics 1 t on 25 ns typ r l = 50 , c l = 35 pf 37 43 ns max v s = 1.5 v/0 v; see figure 19 t off 7 ns typ r l = 50 , c l = 35 pf 7.4 8 ns max v s = 1.5 v; see figure 19 break-before-make time delay, t bbm 22 ns typ r l = 50 , c l = 35 pf 13 ns min v s1 = v s2 = 1 v; see figure 20 charge injection 23 pc typ v s = 1.5 v, r s = 0 v, c l = 1 nf; see figure 21 off isolation ?75 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 22 channel-to-channel crosstalk ?85 db typ s1a to s2a/s1b to s2b; r l = 50 , c l = 5 pf, f = 100 khz; see figure 25 ?73 db typ s1a to s1b/s2a to s2b; r l = 50 , c l = 5 pf, f = 100 khz; see figure 24 total harmonic distortion, thd 0.15 % typ r l = 32 , f = 20 hz to 20 khz, v s = 1.5 v p-p insertion loss ?0.07 db typ r l = 50 , c l = 5 pf; see figure 23 C3 db bandwidth 100 mhz typ r l = 50 , c l = 5 pf; see figure 23 c s (off ) 20 pf typ c d , c s (on) 52 pf typ power requirements v dd = 3.6 v i dd 0.002 a typ digital inputs = 0 v or 3.6 v 1.0 a max 1 guaranteed by design, not subject to production test.
ADG854 rev. 0 | page 5 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to gnd ?0.3 v to +6 v analog inputs 1 ?0.3 v to v dd + 0.3 v digital inputs 1 ?0.3 v to v dd + 0.3 v or 10 ma, whichever occurs first peak current per channel, s or d 500 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current per channel, s or d 300 ma operating temperature range ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c 10-lead mini lfcsp ja thermal impedance, 3-layer board 131.6c/w reflow soldering, pb-free peak temperature 260(+0/?5)c time at peak temperature 10 sec to 40 sec 1 overvoltages at in, s, or d are clamped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. esd caution
ADG854 rev. 0 | page 6 of 16 pin configuration and function description 7 8 s 2 b d 2 3 2 s 1 b d 1 5 6 4 i n 2 v d d i n 1 ADG854 top view (not to scale) 1 0 9 1 g n d s 2 a s 1 a 07087-002 figure 2. pin configuration table 4. pin function descriptions pin no. mneonic description 1, 3, 7, 9 s1a, s1b, s2b, s2a source termin al. this pin can be an input or output. 2, 8 d1, d2 drain terminal. this pin can be an input or output. 4 in1 logic control input. 5 in2 logic control input. 6 v dd most positive power supply potential. 10 gnd ground (0 v) reference. table 5. ADG854 truth table logic (in1/in2) switch a (s1a or s2a) switch b (s1b or s2b) 0 off on 1 on off
ADG854 rev. 0 | page 7 of 16 typical performance characteristics 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 01 2 3456 07087-003 on resistance ( ? ) v d , v s (v) v dd = 4.2v v dd = 4.5v v dd = 5.0v v dd = 5.5v t a = 25c figure 3. on resistance vs. v d (v s ), v dd = 4.2 v to 5.5 v 0 0.5 1.0 2.0 1.5 2.5 3.0 3.5 4.0 07087-004 on resistance ( ? ) v d , v s (v) v dd = 2.7v v dd = 3.0v v dd = 3.3v v dd = 3.6v t a = 25c 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 figure 4. on resistance vs. v d (v s ), v dd = 2.7 v to 3.6 v 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 07087-005 on resistance ( ? ) v d , v s (v) v dd = 5v t a = ?40c t a = +85c t a = +25c figure 5. on resistance vs. v d (v s ) for different temperatures, v dd = 5 v 1.2 1.0 0.8 0.6 0.4 0.2 0 0 0.5 1.0 1.5 2.0 2.5 3.0 07087-006 on resistance ( ? ) v d , v s (v) t a = ?40c v dd = 3.3v t a = +85c t a = +25c figure 6. on resistance vs. v d (v s ) for different temperatures, v dd = 3.3 v 1.1 0.9 0.7 0.5 0.3 0.1 ?0.1 10 20 30 40 50 60 70 80 07087-007 leakage (na) temperature (c) v dd = 5v i d, i s (on) ++ i d, i s (on) ? ? i d, i s (off) +? i d, i s (off) ?+ figure 7. leakage current vs. temperature, v dd = 5 v 0.8 0.6 0.4 0.2 0 ?0.2 10 20 30 40 50 60 70 80 07087-008 leakage (na) temperature (c) v dd = 3.3v i d, i s (on) ++ i d, i s (on) ? ? i d, i s (off) +? i d, i s (off) ?+ figure 8. leakage current vs. temperature, v dd = 3.3 v
ADG854 rev. 0 | page 8 of 16 70 60 50 40 30 20 10 0 0123456 07087-009 charge injection (pc) source voltage (v) v dd = 2.5v v dd = 3v v dd = 5v figure 9. charge injection vs. source voltage 35 30 25 20 15 10 5 0 ?60 ?40 ?20 0 20 40 60 80 100 07087-010 time (ns) temperature (c) t on (3.3v) t on (5v) t off (5v) t off (3.3v) figure 10. t on /t off times vs. temperature 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?16 0.1 1 10 100 1k insertion loss (db) frequency (mhz) 07087-011 t a = 25c v dd = 5v, 3.3v figure 11. bandwidth 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0.1 1 10 100 1k attenuation (db) frequency (mhz) 07087-012 t a = 25c v dd = 5v, 3.3v figure 12. off isol ation vs. frequency 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0.1 1 10 100 1k crosstalk (db) frequency (mhz) 07087-013 t a = 25c v dd = 5v, 3.3v s1a to s1b s1a to s2a figure 13. crosstalk vs. frequency 0.25 0.20 0.15 0.10 0.05 0 100 100k thd + n (%) 1k 10k frequency (hz) 07087-014 v dd = 2.7v v dd = 3.6v v dd = 4.2v v dd = 5.5v figure 14. total harmonic distortion + noise (thd+n) vs. frequency
ADG854 rev. 0 | page 9 of 16 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 100 1k 10k 100k 1m 10m 100m 1g psrr (db) frequency (hz) 07087-015 t a = 25c v dd = 5v, 3.3v figure 15. psrr vs. frequency
ADG854 rev. 0 | page 10 of 16 test circuits sd v s r on = v1/i ds i ds v1 07087-019 figure 16. on resistance sd v s v d i s (off) i d (off) a a 07087-020 figure 17. off leakage sd v d i d (on) nc a 07087-021 figure 18. on leakage d in gnd r l 50 ? c l 35pf v dd v in v out v s v dd v out t on t off 50% 50% 90% 90% 0.1f s1b s1a 07087-022 figure 19. switching times, t on , t off v out v in t bbm t bbm 50% 50% 80% 0v d in gnd r l 50 ? c l 35pf v dd v out v s v dd 0.1f s1b s1a 80% 07087-023 figure 20. break-before-make time delay, t bbm in gnd v dd v s v in v out 1nf v out nc sw on q inj = c l v out sw off v out s1b s1a d 07087-024 figure 21. charge injection
ADG854 rev. 0 | page 11 of 16 v dd v s v dd nc network analyzer s1b s1a gnd off isolation = 20 log d 50? 50? v out r l 50? 0.1f v out vs 07087-025 figure 22. off isolation network analyzer r l gnd v dd v dd v out v s s1a s1b 0.1f d 50? 50? insertion loss = 20 log v out with switch v out without switch 07087-026 figure 23. bandwidth v out v dd v dd gnd v s r l 50 ? r l 50 ? 0.1f 50 ? s1a d s1b channel-to-channel crosstalk = 20 log v out vs network analyzer 07087-027 figure 24. channel-to-channel cro sstalk (s1a to s1b/s2a to s2b) v out 50? 50? 50? v s network analyzer s2a s2b d1 d2 nc nc s1a s1b channel-to-channel crosstalk = 20 log v out vs 07087-028 figure 25. channel-to-channel cro sstalk (s1a to s2a, s1b to s2b)
ADG854 rev. 0 | page 12 of 16 terminology i dd positive supply current. v d (v s ) analog voltage on terminal d and terminal s. r on ohmic resistance between terminal d and terminal s. r flat (on) the difference between the maximum and minimum values of on resistance as measured on the switch. r on on resistance match between any two channels. i s (off) source leakage current with the switch off. i d (off) drain leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. c s (off) off switch source capacitance. measured with reference to ground. c d (off) off switch drain capacitance. measured with reference to ground. c d , c s (on) on switch capacitance. measured with reference to ground. c in digital input capacitance. t on delay time between the 50% and 90% points of the digital input and switch on condition. t off delay time between the 50% and 90% points of the digital input and switch off condition. t bbm on or off time measured between the 80% points of both switches when switching from one to another. charge injection measure of the glitch impulse transferred from the digital input to the analog output during on/off switching. off isolation measure of unwanted signal coupling through an off switch. crosstalk measure of unwanted signal that is coupled from one channel to another because of parasitic capacitance. ?3 db bandwidth frequency at which the output is attenuated by 3 db. on response frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. thd + n ratio of the harmonics amplitude plus noise of a signal to the fundamental.
ADG854 rev. 0 | page 13 of 16 outline dimensions 033007-a 0.40 bsc 1 46 9 p i n 1 i d e n t i f i e r top view bottom view seating plane 0.20 dia typ 0.60 0.55 0.50 0.20 bsc 1.60 1.30 0.55 0.40 0.30 0.35 0.30 0.25 0.05 max 0.02 nom figure 26. 10-lead lead frame chip scale package [lfcsp_uq] 1.30 1.60 mm body, ultrathin quad (cp-10-10) dimensions shown in millimeters ordering guide model temperature range package description package option branding ADG854bcpz-reel 1 ?40c to +85c 10-lead lead frame chip scale package [lfcsp_uq] cp-10-10 c ADG854bcpz-reel7 1 ?40c to +85c 10-lead lead frame chip scale package [lfcsp_uq] cp-10-10 c 1 z = rohs compliant part.
ADG854 rev. 0 | page 14 of 16 notes
ADG854 rev. 0 | page 15 of 16 notes
ADG854 rev. 0 | page 16 of 16 notes ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07087-0-6/08(0)

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